This invention relates generally to the testing of semiconductor integrated circuits (ICs) and devices, and more particularly the invention relates to the multiplexing of test signals to a wafer prober for selectively testing by different devices.
In the electrical probing and measuring of electrical parameters of integrated circuits and devices in semiconductor wafers, a probe card with multiple pins facilitates concurrent access to a large number of circuit contacts in one or more devices in the wafer. Typically one or more probe cards are spaced from the wafer so that “massively parallel” measurements can be made on a single wafer.
In all automated parametric testing of semiconductor devices there is a need to collect large amounts of data from devices on wafers using a minimum set of expensive parametric test equipment to share amongst large numbers of devices. This can be achieved by switching or multiplexing the parametric test equipment output amongst device inputs across the whole wafer, one at a time. Typically this can be achieved by an external multiplexer which requires a bundle of cables to connect to a probe card on an automatic wafer prober, or by a multiplexer that can reside right on top of the probe card on the wafer prober, and which makes contact with a probe card through pogo pins. The disadvantage of the external multiplexer, aside form the high cost of the multiplexer and the added cost of the large number of cables needed to route the signals to a distribution head on top of the wafer prober, is added cable length, which makes the system prone to noise pickup. In addition this cabling scheme introduces stray capacitance into the system, which can damage the components under test. Multiplexing the signals on top of the probe card with traditional multiplexing is very similar in cost to the use of an external multiplexer in that a large number of relays and switches are used, in the construction of the multiplexer, which increases expense.
This is illustrated in FIG. 1 where a parametric tester 10 has N source lines 12 connected through a pin multiplexer 14 which selects pins of a wafer prober 16 to receive the N source lines. Typically the pin selection will vary for different devices (i.e., circuit layouts) in a semiconductor wafer under control of computer 18.